3-Layer ISDB-T Demodulator (ISDBT-D)

The Zaltys Terrestrial Integrated Services Digital Broadcasting Demodulator (ISDBT-D) IP core is a 3-layer ISDB-T hierarchical demodulator compatible with the ARIB STD-B31 standard. The core connects to an RF frontend via one or two fixed-rate ADCs (real or complex baseband) and performs the necessary processing to recover 3 separate transport streams carried on 3 separate layers within an ISDB-T broadcast channel. Sophisticated error-correction and channel equalisation techniques ensure excellent performance whilst ready access to error-rate metrics allows real-time system operation to be monitored and optimised.

Functional blocks include:


  • Radio interface with IF mixer and AGC
  • Sample rate matching channel filters
  • Signal mode detection correlators
  • 2K, 4K or 8K FFT processing
  • Interpolating channel estimator
  • One-tap channel equaliser
  • TMCC decoder with error correction
  • Time and frequency deinterleavers
  • Three independent inner layer decoders
  • Outer Reed Solomon decoder
  • Three independent layer output FIFOs
  • Online BER, MER and PER monitor
  • Optional per-layer PRBS based BERT
  • Optional DSP data capture block


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Technical Features
Full 13-segment ISDB-T demodulator
Compliant with the ARIB STD-B31 standard
Supports 1, 2 or 3 (hierarchical) layers
Auto-detection of mode, guard-interval and bandwidth
Sophisticated algorithms ensure excellent performance
Support for single and dual ADC input schemes
Three separate transport-stream outputs
Extensive error metrics available via register interface
Data capture facility at multiple points through the signal chain
Integral PRBS data decoder aids system integration and link performance measurements
Supports 2K, 4K & 8K FFT sizes (modes 1, 2 & 3)
DQPSK, QPSK, 16QAM & 64QAM demodulation schemes
1, 2, 4, 8, 16 & 32 timing interleaver depths
1/2, 2/3, 3/4, 5/6 & 7/8 code rates
1/4, 1/8, 1/16 & 1/32 guard intervals
Single external SDRAM device - DDR1 or DDR2
Microprocessor controllable via SMPI interface
Fully synchronous design
Available now for Xilinx FPGA
Hardware evaluation board (available extra)