DVB-S2 Demodulator (DVBS2-D)

The Zaltys DVB-S2 Demodulator (DVBS2-D) IP core is a variant of the Zaltys HDRM-D2 Demodulator core which implements a DVB-S2 compliant demodulator. The demodulator accepts I & Q complex baseband samples from an external RF front-end through dual-ADCs. The demodulator output is a sequence of symbols, nominally positioned at the specified constellation points, intended to drive an external LDPC / BCH soft-decision FEC decoder to recover the MPEG transport stream data.

Functional blocks include:

  • Radio Interface (RIF)
  • Decimator(DEC)
  • Timing Recovery(TIM)
  • Adaptive Equaliser (AEQ)
  • Framing Acquisition (FARS)
  • Carrier Recovery (CARS)
  • Control State Machine (FSM)
  • Microprocessor Interface (SMPI)

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Technical Features
Excellent performance
Supports VCM operation
QPSK, 8PSK, 16APSK & 32APSK modulations
Normal and short frame sizes
1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 code rates
Microprocessor controllable via SMPI interface
Data capture and monitoring facilities throughout data path
Fully synchronous design with single clock
Proven in customer applications