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The Zaltys DVB-S2 Demodulator (DVBS2-D) IP core is a variant of the
Zaltys HDRM-D2 Demodulator
core which implements a DVB-S2 compliant demodulator.
The demodulator accepts I & Q complex baseband samples from an external RF front-end through dual-ADCs.
The demodulator output is a sequence of symbols, nominally positioned at the specified constellation points, intended to drive an external LDPC / BCH soft-decision FEC decoder to recover the MPEG transport stream data.
Functional blocks include:
- Radio Interface (RIF)
- Decimator(DEC)
- Timing Recovery(TIM)
- Adaptive Equaliser (AEQ)
- Framing Acquisition (FARS)
- Carrier Recovery (CARS)
- Control State Machine (FSM)
- Microprocessor Interface (SMPI)
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In order to deliver excellent performance, the design utilizes multiple gain control stages within the data path to maximize dynamic range.
Up to four sets of matched root-raised cosine filter coefficients can be incorporated into a given implementation, allowing four excess bandwidth values for the input signal to be selected in software.
All aspects of the timing and carrier recovery are fully programmable, including loop filter coefficients and lock detector thresholds.
In addition, monitoring registers provide a high degree of software visibility for parameters such as frequency offsets, lock levels and SNR estimation.
Applications
The Zaltys DVB-S2 Demodulator (DVBS2-D) core is ideally suited to the following applications:
- Satellite Communications
- Microwave Line-of-Sight
- Broadcast Networks
Delivery Schemes & Outline Costs
The following
Delivery Systems
are available for this core.
A relative price indication is shown - please contact our
Sales Team
for up-to-date pricing.
Devices & netlists are available for the Xilinx range of FPGA devices.
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