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The Zaltys DVB-S2 Modulator (DVBS2-M) IP core is a variant of the
Zaltys HDRM-M Modulator
core which implements a DVB-S2 compliant modulator.
The core accepts an input stream of MPEG2 TS-packets over an ASI interface, and after performing all necessary BB, FEC and PL processing, provides a
stream of complex-valued samples which are pushed to the HDRM-D modulator block (included) for sample-rate conversion and RRC filtering.
Functional blocks include:
- MPEG2 TS alignment recovery and buffering
- Baseband (BB) frame construction
- BCH and LDPC FEC processing
- Physical Layer (PL) frame construction
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The modulator processes a single MPEG2 TS-packet stream and drives a complex baseband output signal to the HDRM Modulator core (included).
Incoming TS-packets are buffered in a 16K-byte ASI input FIFO before being consumed by the internal processing blocks.
A FIFO level signal is available to so that external circuitry can control the flow of packets into the core.
If the FIFO does not contain enough information to allow a BB frame to be constructed the core will send dummy PL frames until ready.
The Zaltys DVB-S2 Modulator core instantiates the Xilinx DVB-S2 FEC Encoder LogiCORE.
Users of our modulator core must therefore possess a licence to the Xilinx core in order to generate a usable design.
Applications
The Zaltys DVB-S2 Modulator (DVBS2-M) core is ideally suited to the following applications:
- Satellite Communications
- Microwave Line-of-Sight
- Broadcast Networks
Delivery Schemes & Outline Costs
The following
Delivery Systems
are available for this core.
A relative price indication is shown - please contact our
Sales Team
for up-to-date pricing.
Devices & netlists are available for the Xilinx range of FPGA devices.
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