DVB-S2 Modulator (DVBS2-M)

The Zaltys DVB-S2 Modulator (DVBS2-M) IP core is a variant of the Zaltys HDRM-M Modulator core which implements a DVB-S2 compliant modulator. The core accepts an input stream of MPEG2 TS-packets over an ASI interface, and after performing all necessary BB, FEC and PL processing, provides a stream of complex-valued samples which are pushed to the HDRM-D modulator block (included) for sample-rate conversion and RRC filtering.

Functional blocks include:

  • MPEG2 TS alignment recovery and buffering
  • Baseband (BB) frame construction
  • BCH and LDPC FEC processing
  • Physical Layer (PL) frame construction

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Technical Features
ASI interface for incoming TS-packets
Microprocessor controllable via SMPI interface
Supports QPSK, 8PSK, 16APSK & 32APSK modulation
Normal and short frame sizes
1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 code rates
Test-mode traffic generator
Fully synchronous design
Two clocks: one system clock, one ASI i/f clock
Suitable for Xilinx FPGA
Proven in customer applications