The DVB-S DSNG FEC Decoder interprets forward error correction information and corrects a data stream according to the DVB and DVB DSNG standards. The design is compliant to the relevant sections of EN 300 421 and EN 301 210.

The Decoder accepts byte wide I and Q soft-decisions from an external demodulator function, and generates byte wide corrected data stripped of any error correction information. The core performs the following operations:

• Derandomisation (to EN 300 421)
• 204/188 (shortened) Reed Solomon Outer Decoder (to EN 300 421)
• Depth 12 Convolutional Deinterleaver (to EN 300 421)
• Convolutional Inner Decoder (K=7)
• QPSK Code Rates of 1/2, 2/3, 3/4, 5/6 & 7/8 (to EN 300 421)
• 8PSK Code Rates of 2/3, 5/6 & 8/9 (to EN 301 210)
• 16QAM Code Rates of 3/4 & 7/8 (to EN 301 210)
• "Parallel to Parallel" & "Parallel to Serial" Decoders (to EN 301 210)
• Symbol Desequencer (to EN 301 210)

N.B. This core makes use of the Xilinx Viterbi Decoder core and the Xilinx Reed Solomon Decoder core, and these cores will need to be licenced separately directly from Xilinx.

Please contact the Sales Team for more information.