Technical Features
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Full 13-segment ISDB-T demodulator
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Compliant with the ARIB STD-B31 standard
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Supports 1, 2 or 3 (hierarchical) layers
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Auto-detection of mode, guard-interval and bandwidth
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Sophisticated algorithms ensure excellent performance
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Support for single and dual ADC input schemes
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Three separate transport-stream outputs
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Extensive error metrics available via register interface
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Data capture facility at multiple points through the signal chain
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Integral PRBS data decoder aids system integration and link performance measurements
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Supports 2K, 4K & 8K FFT sizes (modes 1, 2 & 3)
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DQPSK, QPSK, 16QAM & 64QAM demodulation schemes
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1, 2, 4, 8, 16 & 32 timing interleaver depths
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1/2, 2/3, 3/4, 5/6 & 7/8 code rates
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1/4, 1/8, 1/16 & 1/32 guard intervals
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Single external SDRAM device - DDR1 or DDR2
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Microprocessor controllable via SMPI interface
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Fully synchronous design
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Available now for Xilinx FPGA
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Hardware evaluation board (available extra)
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