3-Layer ISDB-T Modulator (ISDBT-M)
The Zaltys Terrestrial Integrated Services Digital Broadcasting Modulator (ISDBT-M) IP core is a 3-layer ISDB-T hierarchical modulator compatible with the ARIB STD-B31 standard.
The core can process either a single BTS transport stream (containing information for all three layers of the ISDB-T frame structure), a single MPEG transport stream (with user assigned mapping of PID’s to layers), or three independent MPEG transport streams, one for each layer.
It performs all the necessary processing required to output a complex modulated baseband signal to a pair of external DACs.
Functional blocks include:
- Fully Compliant Broadcast Transport Stream (BTS) Interface
- Individual Layer Interfaces with FIFOs
- Reed-Solomon & Convolutional Encoding
- Differential & Coherent Modulation
- Time & Frequency Interleaving
- 2K, 4K or 8K IFFT Processing
- Guard Interval Insertion
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The modulator processes up to three MPEG transport-streams and drives a complex baseband output signal to a pair of external DACs.
A single BTS transport stream can be input to the core, carrying all the information necessary to construct a full 3-layer ISDB-T baseband signal as per ARIB STD-B31.
Alternatively, if single-frequency network operation is not required, a single combined TS stream can be divided and mapped to each layer, or alternatively three separate TS streams can be accepted and fed independently to each layer.
Settings for modulation scheme, FEC code rate, & time-interleaver depth are individually applied to each layer, before the resulting data is frequency-interleaved. Pilot carriers are then added, along with TMCC and AC information.
The resulting 13-segment frame is then passed through an IFFT block, and a programmable guard interval is copied into the result before being sent to the external I & Q DACs.
The bandwidth of the generated signal is directly related to the supplied system clock.
One sample is sent to the external DACs every eight system clock cycles.
- For a 6 MHz ISDB-T bandwidth, the system clock should be 4096/63 (65.01587… MHz)
- For a 7 MHz ISDB-T bandwidth, the system clock should be 2048/27 (75.85185… MHz)
- For a 8 MHz ISDB-T bandwidth, the system clock should be 16384/189 (86.68783… MHz)
An external DDR2 SDRAM device is required to support the BTS interface, time interleaving, and 2 or 3-layer operation.
The device should be compatible with a Micron MT47H32M16 512Mbit DDR2 SDRAM (8M x 16 bit x 4 banks).
Applications
The Zaltys ISDB-T Modulator (ISDBT-M) core is ideally suited to the following applications:
- Broadcast digital TV
- Mobile TV camera
- Outside broadcast unit
Delivery Schemes & Outline Costs
The following
Delivery Systems
are available for this core.
A relative price indication is shown - please contact our
Sales Team
for up-to-date pricing.
Devices & netlists are available for the Xilinx range of FPGA devices.
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VHDL Code
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Technical Features
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Fully SFN compliant 13-segment ISDB-T modulator
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Compliant with the ARIB STD-B31 standard
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Supports 1, 2 or 3 (hierarchical) layers
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BTS interface for Studio Transmitter Link (STL)
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Supports 2K, 4K & 8K FFT sizes (modes 1, 2 & 3)
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DQPSK, QPSK, 16QAM & 64QAM modulation schemes
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1, 2, 4, 8, 16 & 32 time-interleaver depths
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1/2, 2/3, 3/4, 5/6 & 7/8 code rates
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1/4, 1/8, 1/16 & 1/32 guard intervals
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Auxiliary channel (AC) port
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Microprocessor controllable
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Single DDR2 SDRAM interface
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Time windowing reduces effects of OFDM symbol discontinuities
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Test-mode traffic generator
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Transmission bandwidth depends on system clock - 6/7/8MHz all supported
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Flexible input stream configuration - BTS or TS
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Fully synchronous design
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Suitable for Xilinx FPGA
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Hardware evaluation board (available extra)
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