The modulator processes up to three MPEG transport-streams and drives a complex baseband output signal to a pair of external DACs. Incoming transport-stream packets are buffered in 1023-byte layer-interface FIFOs before being consumed by the internal processing blocks. FIFO level signals are available to allow external circuitry to ensure that the FIFOs do not underflow or overflow. The bandwidth of the generated signal is directly related to the supplied system clock. One sample is sent to the external DACs every eight system clock cycles.

• For a 6 MHz ISDB-T bandwidth, the system clock should be 4096/63 (65.01587… MHz)
• For a 7 MHz ISDB-T bandwidth, the system clock should be 2048/27 (75.85185… MHz)
• For a 8 MHz ISDB-T bandwidth, the system clock should be 16384/189 (86.68783… MHz)

Two external SDRAM devices are required, one for time-interleaving and the other for multiple layer operation. If either or both of these features are not required, then the corresponding SDRAM(s) may be omitted. Each SDRAM device should be compatible with an ISSI IS42S16400D-7TL 64Mbit synchronous DRAM (1 Mbit x 16 bit x 4 banks).

Applications
The Zaltys ISDB-T Modulator (ISDBT-M) core is ideally suited to the following applications:

• Broadcast digital TV
• Mobile TV camera
• Outside broadcast unit

Delivery Schemes & Outline Costs
The following Delivery Systems are available for the Modulator core. A relative price indication is shown - please contact our Sales Team for up-to-date pricing. Devices & netlists are available for the Xilinx range of FPGA devices.