The Zaltys High Data Rate Enhanced Demodulator (HDRM-D2) IP core efficiently realizes the digital baseband section of a high performance modem receive path. Using sophisticated DSP techniques, the core can demodulate BPSK, QPSK, OQPSK, 8PSK, 8QAM (3 shapes), 16QAM, 64QAM, 16APSK & 32APSK schemes, all to a high performance level and at high symbol rates.
Functional blocks include:
- Radio Interface including AGC
- Quasi-Zero IF to Baseband Conversion
- Sample Decimation
- Symbol Timing Recovery
- Symbol Rate Blind Adaptive Equaliser
- Carrier Recovery
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The demodulator is highly flexible, supporting continuously variable software-selectable symbol rates of between 4.9kbaud and 40Mbaud, when operating with a 100MHz system/ADC clock rate. This is the typical performance achievable when implementing the design using inexpensive FPGA devices, but increased data rates are possible by targeting the design to higher performance FPGA families which allow an increase in system clock rate. Once configured via the 32-bit microprocessor interface, the demodulator operation is completely automatic.
Applications
The Zaltys High Data Rate Enhanced Demodulator (HDRM-D2) core is ideally suited to the following applications:
- Satellite Communications
- Microwave Line-of-Sight
- Broadcast Networks
- Wired & Optical Links
Delivery Schemes & Outline Costs
The following Delivery Systems are available for the demodulator core. A relative price indication is shown - please contact our Sales Team for up-to-date pricing. Devices & netlists are available for a range of FPGA families, including Xilinx, Altera & Lattice.
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VHDL & Matlab
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Price Range
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